A conventional integrated circuit contains a plurality of patterns of metal lines separated by inter-wiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the metal patterns of vertically spaced metallization layers are electrically interconnected by vias. Metal lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of this type, according to current technology, may comprise eight or more levels of metallization to satisfy device geometry and micro-miniaturization requirements.
A common method for forming metal lines is known as “damascene”. Generally, this process involves forming an opening in the dielectric interlayer, which separates the vertically-spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After an opening is formed, the opening is filled with copper or copper alloys to form a metal line and/or a via. Excess metal material on the surface of the dielectric interlayer is then removed by chemical mechanical polish (CMP).
Although copper has low resistivity and high reliability, it suffers from electro-migration (EM) and stress-migration (SM) reliability issues as geometries continue to shrink and current densities increase. Various approaches are thus explored to solve these problems.
One of the solutions for solving the above-discussed problem is to form a metal cap on the copper. The formation of metal caps greatly improves the reliability of the integrated circuit by reducing the surface migration of the copper lines. It has been found that under stressed conditions, the mean time to failure (MTTF) of the illustrated interconnection structure may be ten times longer than that of an interconnect structure having no metal caps. Part of the reason for the improvement is the reduction of electro-migration. With the metal caps, stress-induced void formation is also significantly reduced.
Metal caps are typically formed using electroless plating, during which the semiconductor wafer, on which the copper lines are formed, is submerged into a metal-ion-containing solution. Metal ions in the solution are selectively deposited on copper, and thus a metal cap is formed on the copper line, but not on the low-k dielectric layer in which the copper line is formed. A problem for this method is that it is difficult to control the thickness uniformity of the metal cap, and sometimes the metal cap cannot cover the entire surface of the copper line well. A method for improving the plating process is thus needed.